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Software based fault tolerance
a survey

Ubiquity, Volume 2006 Issue July | BY Goutam Kumar Saha 


Full citation in the ACM Digital Library

This article aims to present a survey of important software based (or software controlled) fault tolerance literature over the period of 1966 to 2006. Nowadays, fault tolerance is a much researched topic. A system fails because of incorrect specification, incorrect design, design flaws, poor testing, undetected fault, environment, substandard implementation, aging component, operator errors or combination of these causes [1,7]. Modern microprocessors having faster and denser transistors with lower threshold voltages and tighter noise margins make them less reliable [6] but such transistors yield performance enhancements [4,5]. At the same time, such transistors render processors more susceptible to transient faults. Transient faults are intermittent faults that are caused by external events or by the environment [7], for examples, energetic particles [84,93] striking the chip or electrical surges [1,3] etc. Though these faults do not cause permanent faults [2], but they may result in incorrect program execution by inadvertently altering processors' states, signal transfers or stored values on registers etc. If a fault of such type affects program's normal execution, it is considered to be a soft error [2,8,85]. Though programming bugs is considered to be an important reason of the most system failures at present but the recent studies suggest that soft errors are increasingly responsible for system downtime. Computing system is becoming more complex and is getting optimized for performance and price but not for availability. This makes soft errors an even more common case. Using denser, smaller and lower voltage transistors has the potential threats to be more susceptible [92] to such increased transient errors. Soft errors are the errors, which occur because of the unintended transitions of logic state in a circuit typically caused by external source of ionizing radiations. The ionization creates excess free carriers, which recombine with the stored charges, thereby corrupting the state of transistor [8]. Device scaling, reduction in feature size and voltage levels of the transistor, along with high density transistors have increased the risk of hardware faults due to soft errors [85]. Research in [6] predicts that soft error rate (SER) per chip of logic circuits will increase nine orders of magnitude from 1992 to 2011 and at that point will be comparable to the SER per chip of unprotected memory elements [8]. Works in [9,10] have verified the soft error rate (SER) of 52000 FIT (1 FIT equals 1 failure in 109 Hours) on a 16 Mbit DRAM chip. A system with hundred such chips will experience a fail rate of almost one per week. Studies in [9,10] also claimed that a typical processor's silicon can have a soft-error rate of 4000 FIT, of which 50% will affect processor logic and 50% the large on-chip cache [8]. Until now techniques such as Error Correction Codes (ECC) have been used to correct errors in main memory and system interconnects. Work in [11] states that it is difficult to shield systems effectively from transient faults using fault avoidance techniques. It suggests employing some other means, which are based on fault- masking [27,28] and fault recovery through check pointing or rollback etc [20,21,22,24,75,76,77,88] in order to assure appropriate levels of transient fault tolerance or insensitivity to transient faults. Having analyzed this problem, the study in [11] identifies critical design points and outlines some practical solutions that refer to efficient on-line detectors (detecting errors [24,25,56,61,62,78,80,87,89,91] during the system operation) and error handling procedures [13,14,15,17,19,23]. This framework provides a basis for understanding transient fault problems in digital systems. It can be helpful in selecting optimum techniques to mask or eliminate transient fault effects in developed systems [11,12].

Studies in [16] state that most of the microprocessor-based systems provide little or no checking for failures in the microprocessor itself. These systems rely on the high reliability of VLSI and the inbuilt run-time checks (e.g., virtual memory protection and illegal instruction exceptions) to ensure data integrity. Work in [26] states that reliability of microprocessors is dictated by the faults that cause a reduction of it - Design faults, manufacturing faults and operational faults. Work in [16] presents a model to analyze systems' vulnerability [18] to undetected data corruptions due to transient faults. Though time redundancy provides us dependability against transient faults, however, works in [72,73,74,79] show that this scheme is also effective against permanent faults. Work in [29] has the intention of NASA's Remote Exploration and Exploration (REE) project to use commercial off-the-shelf, scalable, low-power, fault-tolerant, high-performance computation in space. It has observed that most of the faults caused by the radiation environments in regions of space of interest to REE (Deep Space, Low Earth Orbit) are transient, single event etc. Some of these faults can cause errors at different application levels. The study [29] shows that system and applications software can potentially detect and correct some or many of these errors by using different software fault tolerance approaches such as replication, voting, and masking with a focus on algorithm-based fault-tolerance [7, 31,32,33,34,35,37] or by using a combined software and hardware approaches [30,36,38] such as fault avoidance, redundancy, masking, and reconfiguration. However, such approaches allow trade-offs between reliability, power, cost, and computation power for spacecraft in a low-to-moderate radiation environment [29]. The task of fault detection (for example, through algorithm based fault tolerance (ABFT) [32,81] or through assertions [19, 31] etc.) and recovery becomes easier when we make a system as simple as possible as correctly stated "A system should be as simple as possible in order to achieve its required function-and no simpler" in [30]. The software implemented fault tolerance (SWIFT) schemes [2,17,27,90] aim to increase reliability by inserting redundant code to compute duplicate versions of all register values and inserting validation instructions before control flow and memory operations [2]. The redundant and validation instructions are inserted by the compiler and are used to increase the reliability of systems without any hardware requirements. Again, the studies in [40, 41, 42, 43, 82] aim to tolerate errors in program control flow that account for 33%-77% of all errors. Work in [45] aims to treat software fault-tolerance as a robust supervisory control (RSC) problem and propose a RSC approach to software fault-tolerance. In this approach the software component under consideration is treated as a controlled object that is modeled as a generalized Kripke structure or finite-state concurrent system [44,45].

We have several software fault tolerance schemes as proposed in [46,47,48,49,50] are based on software design diversity in order to tolerate software design bugs. They include the recovery block scheme (RBS) programming, consensus recovery block programming, N-version programming (NVP), N Self-checking programming (NSCP) and data diversity programming etc. The major ideas underlying these fault-tolerant schemes are redundancy and diversity, or diverse redundancy. After the design task is over, a fault-tolerant system needs to be evaluated with respect to a system's specifications either on using a Markov model (an analytical model) to determine a system's possible states and the probable chances of states transitions, or by fault injection into a simulated or into a real system [7,39,51,52,53,54,55,57,58,59,60,63,65] for fault coverage etc. Though multi-version or N-version programming is considered as a method for increasing the overall dependability [64,66,67,68,69,70] of safety-critical systems. However, the increased cost of using this approach may mean that this increase in dependability is not worth the extra expense involved. Analytical results from experiments carried out in [70] show that "(a) a single-version system [86] is much more dependable than any individual version of the multi-version system, and (b) despite the poor quality of individual versions, the multi-version method still results in a safer system than the single-version solution. Although these results could not be considered conclusive in the general sense." However, an enhanced single - version - programming scheme (using a kind of robust programming approach appropriate to an application) often shows dependable result in a non-safety critical application [17,71,83] without an extra expense on hardware and diversified software.

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About the Author
Goutam Saha is an associate editor of Ubiquity.

Source: Ubiquity Volume 7, Issue 25 (July 5, 2006 - July 10, 2006 )

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